After reading my most recent print feature article on flash memory-based solid-state drives published late last November, you hopefully came away from it with an appreciation for the media controller’s critical role in determining the drive performance, power consumption, price, reliability and other important variables. Specifically, the controller manages:

• How much information is actually written to the not-unlimited-cycling flash memory array for a given-sized incoming data payload from the system (i.e. the write amplification factor)
• How intelligently a sequence of file writes, updates and deletions is spread across the array, to prevent block-cycle ‘hot spots’
• How quickly commands and/or data are transferred between any one flash memory chip in the array and the controller, and between the controller and the system (the latter factor rationalizing, for example, the PCI Express bus employed by some SSDs to alleviate SATA bottlenecks)
• How many flash memory components in the array are simultaneously read and/or written, trading off cumulative performance versus cumulative power consumption
• The type and amount of error detection and correction employed to counteract the otherwise corrupting and crippling effects of flash memory ’soft’ and ‘hard’ errors, and
• The diversity of flash memory suppliers (and devices and densities within each supplier’s product line) comprehended by the controller

SandForce’s latest-generation SF-2000 controller series, which is sampling now with chip production scheduled for year end (and with SSDs based on it subsequently forecasted available for sale one quarter later) exemplifies advancements made in these areas. As Anandtech’s writeup notes, they retain a strong lineage to prior-generation SF-1000 and SF-1500 products, which isn’t necessarily a bad thing. The SF-2000’s predecessors suffered from no shortage of firmware- and hardware-based glitches, which company Senior Director of Product Marketing Kent Smith assures me have now been rectified with fixes automatically applicable to the new products as well. Ideally, the SF-2000 products’ new features won’t, due to more robust testing both within SandForce and its partners’ labs, lead to new bugs. And those new features will, if the company’s results predictions are even remotely accurate, put the SF-2000 series in a strong competitive position versus competitors such as Indilinx and Marvell, as well as homegrown controllers developed by companies such as Intel.

At the moment, SandForce has released details on its initial four family members:

The base SF-2000 controller beefs up the system interface (versus its predecessors) to SATA’s 6 Gbps variant, along with up to 32 NCQ (native command queuing) entries. As such, it’ll allow other manufacturers’ SSDs to match Micron’s drives’ currently unique 6 Gbps SATA capabilities. It also supports the newer Toggle and ONFI 2 NAND flash memory interface options, which speed information transfers between the controller and storage array. And it can ‘activate’ (i.e. simultaneously read from and/or write to) up to twice as many flash memory die as could the SF-1000 and SF-1500 controller generations.

All of this enhanced controller potential translates to, according to SandForce, up to 60,000 IOPS (input/output operations per second) for random read and write transfers (4 KByte data packets), along with up to 500 MByte/sec speeds for sequential reads and writes. And here’s the capper…these estimates are for 34 nm MLC (multi-level cell) flash memory, not for the inherently faster (albeit costlier on a per-bit basis) SLC (single-level cell) devices:

The SF-2300 (”around $50″ in single-unit pricing, with “quantity discounts available”) builds on the SF-2000 foundation with operation over the industrial temperature range. The SF-2500 is an enterprise-targeted device, with a real-time AES-256 encryption ‘engine’ (up from AES-128 on prior-generation offerings) and ‘double encryption’ support i.e. the ability to configure unique passwords for different regions of the SSD’s total address range. And the SF-2600 (”around $150″, again single-unit pricing) takes initial tentative steps towards full SAS support. Regular readers may remember me pointing out, in the recent review of Micron’s third-generation and Marvell-based enterprise SSDs, that a SAS-to-SATA external bridge chip was required to comprehend the all-important SCSI command set. The SF-2600 is similar in this respect. But it embeds performance-preserving support for non-512 byte sectors (i.e. 520, 524, 528 and 4 KByte sectors, the latter with an added data integrity field) common in SAS implementations, via hardware write-organization alignment ‘hooks’.

Currently, at least, all SF-2000 family members leverage a common silicon design, with specific product features predominantly-to-completely differentiated via firmware variation. And they all support EDAC (error detection and correction) at up-to-55-bit BCH code levels (versus prior generations’ 24-bit BCH code capabilities), which SandForce brands as RAISE (Redundant Array of Independent Silicon Elements), and commensurate with the controllers’ cognizance of extremely low cost but commensurately low reliability 3-bit-per-cell MLC flash memory. This enhancement led to perhaps the most interesting aspect of my conversation with SandForce’s Smith two-plus weeks back.

EDAC, of course, requires incremental storage for the associated parity data structures. I asked Smith if the flash memory component (and SSD subsystem) industry was yet (or would soon be) at the point where the increasing storage capacities at a given price, enabled by iterative MLC generations and lithography shrinks, were completely counteracted by the increasing amount of storage that had to be reserved for EDAC, spare blocks, and the like due to the increasingly unreliable flash memory media. He responded that this thankfully wasn’t yet the case, and that it was up to SandForce, its controller competitors and its flash memory component partners to ensure that this dour forecast never came to pass.